module adder4(cout,sum,ina,inb,cin);
output wire       cout;
output wire [3:0] sum;
input  wire [3:0] ina, inb;
input  wire       cin;
assign {cout, sum} = ina + inb + cin;
endmodule

`timescale 1ns/1ns
module adder_tp; //测试模块的名字
reg[3:0] a,b; //测试输入信号定义为 reg 型
reg cin;
wire[3:0] sum; //测试输出信号定义为 wire 型
wire cout;

adder4 adder(cout,sum,a,b,cin); //调用测试对象

initial begin 
    for(integer i=0; i<=15; i=i+1) begin 
        a = i;
        b = i;
        cin = 0;
        #5;
        cin = 1;
        #5;
    end
end

initial begin //定义结果显示格式
    $monitor($time,,,"%d + %d + %b={%b,%d}",a,b,cin,cout,sum);
    #160 $finish;
end

endmodule